ETSOI is a leading candidate for continuous scaling of planar Si technology. One consideration to improve performance and reduce series resistance in ETSOI is the use of raised source drain (RSD) epitaxy.
For Poly-SiON gates it has been demonstrated that using an extension-last integration scheme, where extension implants are activated with a diffusion-less laser anneal, reduces the series resistance penalty. Reference in this regard can be made to, for example, A. Majumdar et al., Elec. Dev. Lett. V29 (5), 515-517, 2008.